Davies, U.S. Pat. No. 4,960,723, describes a method for making a self-aligned vertical field effect transistor wherein a silicon nitride sidewall spacer is formed around a polysilicon gate and an oxide spacer is formed covering the nitride sidewall spacer. Using the oxide spacer as a mask, a portion of the source is etched to expose a portion of the silicon substrate, following which the oxide spacer is removed. The contact area between the source and source electrode is thereby increased.
Lin, U.S. Pat. No. 5,498,555, discloses a method for making a horizontal FET having first spacer elements of polysilicon on the vertical sidewalls of the gate electrode and second spacer elements of silicon dioxide on the first spacer elements, the intent being to improve performance and provide immunity against hot carrier effects.
Su et al., U.S. Pat. No. 5,208,472, discloses a horizontal MOS device having two layers of dielectric film on the edge of the gate; the device is intended to have low junction leakage and reduced shorting from gate to source/drain.
Blanchard, U.S. Pat. No. 5,663,079, describes a method of making MOS-gated, double diffused semiconductor devices. In one embodiment, a nitride spacer layer is used to separate an implanted and diffused deep body region from the gate region, then removed by etching.
Lin, U.S. Pat. No. 5,668,065, discloses a process for simultaneously forming silicide-based self-aligned contacts and local interconnects in a horizontal semiconductor device. Oxide spacers adjacent the gate provide a lightly doped drain region within the drain region adjacent the gate and also isolate the gate from a subsequently formed self-aligned source region contact.
Tsai et al., U.S. Pat. No. 5,702,972, describes a method of reducing source/drain resistance in the fabrication of a horizontal semiconductor device, wherein first spacers of oxide are formed on the sidewalls of the gate electrode, and second spacers of nitride are formed on the first spacers. Following implanting of heavily doped source/drain regions, the second spacers are removed.
The disclosures of the just discussed six patents are incorporated herein by reference.